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FRX130D, FRX130R, FRX130H
April 1998
Radiation Hardened N-Channel Power MOSFETs
Description
The Intersil has designed a series of SECOND GENERATION hardened power MOSFETs of both N-Channel and P-Channel enhancement types with ratings from 100V to 500V, 1A to 60A, and on resistance as low as 25m. Total dose hardness is offered at 100K RAD (Si) and 1000K RAD (Si) with neutron hardness ranging from 1E13n/cm2 for 500V product to 1E14n/cm2 for 100V product. Dose rate hardness (GAMMA DOT) exists for rates to 1E9 without current limiting and 2E12 with current limiting. This MOSFET is an enhancement-mode silicon-gate power field effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to exhibit minimal characteristic changes to total dose (GAMMA) and neutron (no) exposures. Design and processing efforts are also directed to enhance survival to heavy ion (SEU) and/or dose rate (GAMMA DOT) exposure. This part may be supplied as a die or in various packages other than shown above. Reliability screening is available as either non TX (commercial), TX equivalent of MIL-S19500, TXV equivalent of MIL-S-19500, or space equivalent of MIL-S-19500. Contact the Intersil High-Reliability Marketing group for any desired deviations from the data sheet.
Features
* 6A, 100V, rDS(ON) = 0.180 * Second Generation Rad Hard MOSFET Results From New Design Concepts * Gamma - Meets Pre-RAD Specifications to 100K RAD (Si) - Defined End-Point Specs at 300K RAD (Si) and 1000K RAD (Si) - Performance Permits Limited Use to 3000K RAD (Si) * Dose Rate - Typically Survives 3E9 RAD (Si)/s at 80% BVDSS - Typically Survives 2E12 if Current Limited to IDM * Photo Current - 1.50nA Per-RAD (Si)/s Typically * Neutron - Maintain Pre-RAD Specifications for 3E13 Neutrons/cm2 - Usable to 3E14 Neutrons/cm2
Ordering Information
PART NUMBER FRX130D1 FRX130D3 FRX130R1 FRX130R3 FRX130R4 FRX130H4 PACKAGE 18 Ld CLCC 18 Ld CLCC 18 Ld CLCC 18 Ld CLCC 18 Ld CLCC 18 Ld CLCC BRAND FRX130D1 FRX130D3 FRX130R1 FRX130R3 FRX130R4 FRX130H4
Symbol
D
G
S
Package
18 LEAD CLCC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
3144.3
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FRX130D, FRX130R, FRX130H
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified FRX130D, R, H 100 100 6 4 18 20 11.4 4.5 0.09 18 6 18 -55 to 150 300 UNITS V V A A A V W W W/oC A A A oC oC
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulsed Avalanche Current, L = 100H, (See Test Figure). . . . . . . . . . . . . . . . . . . . . . IAS Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS Pulsed Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJC, TSTG Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL (Distance >0.063in (1.6mm) from Case, 10s Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IGSSF IGSSR IDSS1 IDSS2 IDSS3 IAR VDS(ON) rDS(ON) td(ON) tr td(OFF) tf Qg(TH) Qg(ON) QgM VGP QgS QgD VSD trr RJC RJA Free Air Operation ID = 6A, VGD = 0 I = 6A; di/dt = 100A/s VDD = 50V, ID = 6A IGS1 = IGS2 0 VGS 20 TEST CONDITIONS ID = 1mA, VGS = 0V ID = 1mA, VDS = VGS VGS = +20V VGS = -20V VDS = 100V, VGS = 0 VDS = 80V, VGS = 0 VDS = 80V, VGS = 0, TC = 125oC Time = 20s VGS = 10V, ID = 6A VGS = 10V, ID = 4A VDD = 50V, ID = 6A Pulse Width = 3s Period = 300s, Rg = 25 0 VGS 10 (See Test Circuit) MIN 100 2.0 1 17 32 3 3 8 0.6 TYP MAX 4.0 100 100 1 0.025 0.25 18 1.130 0.180 30 100 ns 200 100 4 70 128 12 14 nc 32 1.8 400 11 250 V ns
oC/W
UNITS V V nA nA A
Drain to Source Breakdown Voltage Gate Threshold Voltage Gate-Body Leakage Forward Gate-Body Leakage Reverse Zero Gate Voltage Drain Current
Rated Avalanche Current Drain to Source On-State Volts Drain to Source On Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate-Charge Threshold Gate-Charge On State Gate-Charge Total Plateau Voltage Gate-Charge Source Gate-Charge Drain Diode Forward Voltage Reverse Recovery Time Junction To Case Junction To Ambient
-
A V
nc
V
2
FRX130D, FRX130R, FRX130H Typical Performance Curves
Unless Otherwise Specified
8 ID, DRAIN (A)
OPERATION IN THIS AREA IS LIMITED BY rDS(ON) ID, DRAIN (A)
6
10
4
2 10ms FRX130 0 100 50 CASE TEMPERATURE (TC) FRX130 50 VDS DRAIN-TO-SOURCE (V) 100
FIGURE 1. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
FIGURE 2. SAFE OPERATING AREA CURVE CASE TEMPERATURE = 25oC
80 NORMALIZED rDS(ON) 4 RATED BVDSS 3 100V 2 50V 500V 200V
50 ID, DRAIN (A)
30
20
FRX130 100 500 TIME OF INDUCTIVE DISCHARGE (s) 1E13 1E15 1E14 FLUENCE - NEUTRONS/cm2
FIGURE 3. TYPICAL UNCLAMPED INDUCTIVE SWITCHING FAILURE ONSET AVALANCHE MODE
FIGURE 4. NORMALIZED ON-RESISTANCE vs NEUTRON FLUENCE N-CHANNEL
DRAIN CURRENT (A)
100
LIMITING INDUCTANCE (H)
1E-4
ILM = 10A ILM = 30A
10
1E-5 ILM = 100A ILM = 300A 1E-6
1
FRX130 1E8 1E9 GAMMA DOT - RAD (Si)/s 1E10 30 100 DRAIN SUPPLY (V)
GAMMA DOT 300
FIGURE 5. TYPICAL PHOTO CURRENT vs GAMMA RATE
FIGURE 6. DRAIN INDUCTANCE REQUIRED TO LIMIT GAMMA DOT CURRENT TO ILM
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FRX130D, FRX130R, FRX130H Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS WHEN IAS IS REACHED VDS L + CURRENT I TRANSFORMER AS BVDSS tP IAS + VDD VDS VDD
-
VARY tP TO OBTAIN REQUIRED PEAK IAS VGS 20V
50
DUT 50V-150V 50 tAV
0V
tP
FIGURE 7. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 8. UNCLAMPED ENERGY WAVEFORMS
VDD
tON tD(ON)
tOFF tD(OFF) tR tF 90%
RL VDS VGS = 12V DUT 0V RGS
VDS
90%
10%
10%
90% VGS 10% 50% PULSE WIDTH 50%
FIGURE 9. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 10. RESISTIVE SWITCHING WAVEFORMS
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FRX130D, FRX130R, FRX130H 18 Pin CLCC
18 PIN CERAMIC LEADLESS CHIP CARRIER
E
INCHES SYMBOL A b
R1
MILLIMETERS MIN 2.34 0.51 6.99 4.45 1.78 8.64 6.10 2.42 MAX 2.84 0.76 7.49 5.46 2.03 9.14 7.11 2.66 NOTES 4 4
MIN 0.092 0.020 0.275 0.175 0.070 0.340 0.240 0.095
MAX 0.112 0.030 0.295 0.215 0.080 0.360 0.280 0.105
D D1 D2 E E1 E2
D
R
e L
0.050 BSC 0.085 0.035 0.007 0.003 0.115 0.055 0.017 0.013
1.27 BSC 2.16 0.89 0.18 0.08 2.92 1.39 0.43 0.33
A
L1 R R1
SEATING PLANE
NOTES: 1. No current JEDEC outline for this package. 2. All exposed metallized areas shall be plated with a minimum of 50 microinches of gold over nickel unless otherwise stated. 3. Metallized castellations shall be connected to the seating plane and extend upward toward top of package. 4. Corner shape (notch, radius, square, etc.) may vary at the manufacturer's option. 5. Unless otherwise specified, a minimum clearance of 0.010 inches (0.25mm) shall be maintained between all metallized areas. 6. Controlling dimension: Inch. 7. Revision 1 dated 6-93.
E1 E2
D2 D1 1 2 L1
e
b
L
ELEMENT GATE DRAIN SOURCE
PAD A B C 5
PINS CONNECTED
1, 2, 3, 4, 16, 17, 18 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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